REPORT NUMBER 6
‘State Machines and Code Generators’
The report presented is the sole work of the author. None of this report is plagiarised (in whole or part) from a fellow student's work, or from any un-referenced outside source.
PRACTICAL 6: STATE MACHINES AND CODE GENERATORS
AIM:
INTRODUCTION:
This laboratory is about the design, implementation, and testing of a state machine counter and a pulse train generator. The circuits will use JK flip-flops and logic gates to implement the necessary logic operation of the problem. The ICs used are the 7474 JK flip-flops and the 7400 NAND gates . The state machine counter has to follow a State Transition Diagram that is defined in the succeeding sections.
APPARATUS
Electronic Laboratory Equipment.
PROCEDURE:
Design, Build, and Test a three bit synchronous State Machine counter, using JK flip-flops in the Data Mode, that produces the sequence shown in the following State Transition Diagram.
The S input will be a logic level obtained from one of the digital trainer switches, and the output will be attached to the digital trainer LEDs.
Note: It is always best to utilise NAND gates only in the design.
DESIGN:
The design process consists of the state transition diagram, state transition table, K-maps simplification, logic equation generation, and then the logic gate circuit implementation. The AND/OR/NOT logic gate implementation is straightforwardly converted into NAND-only implementation.
KARNAUGH MAPS
CIRCUIT AND/OR DIAGRAM
CIRCUIT NAND/NAND DIAGRAM
RESULTS:
WIRING DIAGRAM
VERIFY OPERATION
S = 0 S = 1
DISCUSSION:
The JK flip-flops are able to preserve its current state, and are able to react accordingly for its future state. This property of JK flip-flops can be used as a mechanism to save memory. The State Machine is able to utilize this memory mechanism in order to operate as desired or as needed. Moreover, the State Machine is also able to operate as a non-standard-counter which might be required for particular applications. The transitions of the states for a particular set of input might be a little more complex than a simple standard “1, 2, 3” counter. Thus, the JK flip-flops are used to save previous states, and then compute for future states. The clock pulse is required so that the flip-flops are constantly synchronized with the input.
Data Mode is used for the JK flip-flop to work as a memory-saving mechanism. The State Machine designed might be used in applications that require memory. For example, the S input is an input in a calculator stack. The State Machine should be able to store in memory whatever the calculator user is pressing (a number, an operation, etc.). Each detected press on the calculator can lead to a finite number of possible states, and these states are defined by a state transition diagram. The JK flip-flop outputs control the display, and the internal computations to be implemented by the calculator.
DC=B+C
DB=SA+C
DA=S+C
Because of this, the design is simplified to consist of 8 logic gates (NAND gates), and 3 JK flip-flops (1 flip-flop for each state).
The designed state machine counter is observed to have followed the State Transition Diagram. The State Transition Table of the implemented circuit is consistent with ‘NEXTSTATE’ column of the expected State Transition Table.
CONCLUSION:
The State Machine Counter was successful in implementing the pre-defined State Transition Diagram. The JK flip-flops in Data Mode were able to save memory in order that the states and the transitions are achieved. The K-map minimization was able to achieve a logic circuit that only required 8 NAND gates and 3 JK flip flops.
REFERENCES:
Texas Instruments, Inc. 1988, DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR, Dallas, TX, viewed 26 May 2016, <http://www.ti.com/lit/ds/symlink/sn5474.pdf>.
Texas Instruments, Inc. 2003, QUADRUPLE 2-INPUT POSITIVE-NAND GATES, Dallas, TX, viewed 26 May 2016, <http://www.ti.com.cn/cn/lit/ds/symlink/sn74ls00.pdf>.
