MULTIPLEXERS AND DEMUMULTIPLEXERS
ELEC201
Digital Electronics
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Objectives
The objectives of this lab include:
Introduction
A multiplexer is a crucial digital circuit that is capable of selecting a single digital signal out of a set or group of signal at its input and passes that signal to its output. It functions as a more as a rotary switch that switches connects one input to the output at a time. On the other hand, the multiplexer does the exact opposite function; it passes multiple digital signal inputs through one of a set or group of outputs. Through multiplexers, several signals can be sent over a single channel as in the case of the TV transmission system, whereby, through a single coaxial cable, several channels can be received.
A multiplexer, simply referred to as a MUX, is a data selector of sorts as it selects one data stream out of a group of them. It is a combinational circuit with more than one input lines but has a single output line, and a set of more than one select lines that serve to select which line is passed on to the output. Some multiplexer integrated circuits (ICs) have the capability of providing complementary outputs. It is noteworthy that multiplexers commonly have the ENABLE (EN) and the STROBE inputs that should be active for the multiplexer to perform the operations for which it was designed. Multiplexers are designed to select or pick up binary information form one of the many inputs depending on the logic status of the select line inputs and the routes to the output. With n selection lines, it is possible to have 2n input lines in the multiplexer, in which case the multiplexer will be a 2n:1 multiplexer or a 2n x 1 multiplexer.
Where n=2, the multiplexer realized is a 4:1 multiplexer. Such a multiplexer can be represented as in the figure below:
Figure 1
10, I1, 12, I3 and I4 represent the inputs, the select lines are represented by X0 and X1 and the output by Since the select lines are selected depending on the logic of the select lines X0 and X1, the following truth table represents that of the 4:1 multiplexer.
4:1 Multiplexer Truth Table
The inputs are represented by D0- D7, the select lines by A, B and C, and the outputs by Y and W. The truth table of the 8:1 multiplexer is as shown below:
For a 2-to-1 multiplexer (below) has the combinational logic shown below. This is derived from the truth table that is shown also below.
Figure 2
The circuit desirable is achieved from the following generalizations: if S=0, the output Y= I0, and if S= 1, the output Y = I1. As such, the inputs I0 and I1 are selected if S=0 and if S=1 respectively. This can be extended to the 4-to-1 multiplexer and on to higher order multiplexer from which Boolean expressions can be derived and circuits built therefrom as shown in the figure below.
The Boolean expression derived from the 4-to-1 Multiplexer is as shown below:
This is an illustration of how the 4-to-1 multiplexer is built out of gates. For the inputs 10, I1, 12, I3 and I4, the select lines will bear the input combinations: 00, 01, 10, and 11 respectively. The Boolean Expressions for the 8-to-1 multiplexer is as follows:
The resultant circuit from the above Boolean Equation is as shown below:
Demultiplexers
Demultiplexers are digital devices made up of combinational logic circuits that have a single input, n select lines, and 2n output lines. The information is fed from a single input and channeled to one of the many outputs of the demultiplexer. Which output line will carry the input signal is decided by the bit status of the select lines. From a demultiplexer, a decoder can be achieved easily as it presents a special case of a demultiplexer that has no input line.
An example of a 1-to-4 demultiplexer is as shown below:
Figure 5
The following is the 1-to-4 multiplexer truth table:
As can be seen the demultiplexer can be derived form a combinational circuit and serves the purpose of decoding information from n inputs to a possible 2n output lines.
Procedure
- Run the MultiSim program and load E9B-1.ms7 circuit.
- The circuit is a 2:1 multiplexer. The S-input selects which of the two inputs A or B will be channeled to the output. The S input selects only one of the AND gates at a time due to the use of the NOT gate. The truth table for a 2:1 multiplexer is as shown below.
Figure 6
When the S input is high, pressing A does not cause any change to the output. Press S to make the S input low. When S is low, pressing key A makes the output follow the state of input A.
Figure 7
Figure 8
When the input S is low, if key B is pressed repeatedly it is observed that the output does not follow the input B.
Changing the input S to high and then pressing key B repeatedly, then the output is seen to follow the input B.
Figure 9
Figure 10
- A 4:1 multiplexer selects one of four inputs using two select inputs S0 and S1. This multiplexer can be constructed using three 2:1 multiplexers. The connections are made such that:
If S1S0=00, then F= A
If S1S0=01, then F= B
If S1S0=10, then F= C
If S1S0=11, then F= D
Figure 11
- Load circuit E9B-2.ms7 that shows a simpler way of making a 4:1 multiplexer. Connecting logic switches and to the inputs A, B C, D, S0 and S1, it can be shown that the output as follows.
If S1S0=00, then F= A
If S1S0=01, then F= B
If S1S0=10, then F= C
If S1S0=11, then F= D
This is similar to the circuit constructed in step 3 above.
- It is often necessary to use more than one multiplexer in a circuit, enabling only one at a time. This can be implemented by adding an enable input E as shown in the figure below.
Figure 12
When the enable input is low, the output F is low regardless of the state of inputs A, B, C, D.
When the enable input is high, the output F follows the inputs A, B, C, D as selected by the inputs S0, and S1.
- MultiSim has a number of 741xx series multiplexer packages. These packages include 74150, 74151, 74153, and 74157.
Load the 74151, which is an 8:1 multiplexer from its location in the TTL bin.
Connect a word generator to the inputs D0 to D7 and an SPDT switch to the select inputs A, B, and C.
Figure 13
If the 3 select inputs are all low, the output follows the input D0. This is shown by the logic analyzer which clearly shows the output 1 and 13 are alike.
Figure 14
If the A input is high, and inputs B and C are low, the output follows the input D1. This is clearly shown by logic analyzer as the input D1 (pin2) and the output (pin 13 on the logic analyzer) have the same pattern.
Figure 15
- Replace 74151 with the 74150 16:1 multiplexer.
Run the simulation.
The output when all select inputs are low is a compliment of the E0 input as shown by the logic analyzer.
Figure 16
Replace the 74150 with 74153 dual 4:1 multiplexer.
Run the simulation.
When both inputs are low, the output follows the 1C0 input.
Figure 17
- Locate other multiplexers in the TTL parts bin. These are the
- 74152AN, which is a data selector.
- 74152AJ also a data selector.
The difference of these parts with those listed in Table 9B is that
- Load E9B-3.ms7 circuit. The circuit shows a 1:2 demultiplexer. The inputs S0 andS1 determine which output Y0 and Y1 the data D is connected. The truth table for the demultiplexer is:
A demultiplexer does the reverse of a multiplexer. It expands one signal into multiple signals.
When the select input S is high, the data in input D is channeled to output Y0
Figure 18
When the select input S is low, the data in input D is channeled to the output Y1
Figure 19
- The 74139 demultiplexer contains two individual two-line to four-line decoders.
The 74154 demultiplexer uses a 4-line to 16-line decoder to channel four binary coded inputs into one of 16 mutually exclusive outputs when both the strobe inputs are low.
The 74155 features a dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address inputs.
- Additional demultiplexer packages contained in MultiSim TTL bin parts are
- The 74156 which e contains two 2-to-4 demultiplexers.
- The 74159 that contains a 4-line to 16-line decoder that decodes four binary coded inputs into one of sixteen mutually exclusive open-collector outputs when both the strobe inputs are low.
These packages differ from those contained in Table 9B.4 in the following ways.
- The 74154 and the 74159 are both 4:16 demultiplexers but the 74154 decodes 4 binary coded inputs into one of sixteen mutually exclusive outputs while the 74159 decodes the 4 binary coded inputs into 16 mutually exclusive open collector outputs when both input probes are low.
- The 74156 and the 74139 are both 2:4 demultiplexers but the 74139 contains two individual 2-line to 4-line decoders with fully buffered inputs, each representing a normalized load to the driving circuit.
Discussion
- Compare the gate counts for the two 4:1 multiplexer circuits in step 3 and 4.
The circuit in step 3 has 11 gates, while that in step 4 has 7 gates. The one in step 4 is therefore much more cost efficient and reliable.
- How to make 64:1 multiplexer out of the standard multiplexer packages.
The number of select pins required is determined using log2 (n) where n is the number of inputs which in this case is 64.
Log2 (64) =16.
The multiplexer would require 16 select pins. These 16 select pins should be implemented using a 1:16 decoder. Thereby implementing a 16:1 multiplexer.
Figure 20
This would require five 1:8 demultiplexers. Connect one 1:8 demultiplexer to the input.
Connect four of the outputs to four 1:8 demultiplexers. In total, a 1:32 demultiplexer has been constructed.
References
Wakerly, J. F. (2000). Digital design: Principles and practices. Upper Saddle River, N.J: Prentice Hall.
Balabanian, N., & Carlson, B. (2001). Digital logic design principles. New York: Wiley.
