REPORT NUMBER 3
PRACTICAL 3: LOGIC GATE CHARACTERISTICS
The report presented is the sole work of the author. None of this report is plagiarised (in whole or part) from a fellow student's work, or from any un-referenced outside source.
PRACTICAL 3: LOGIC GATE CHARACTERISTICS
AIM:
INTRODUCTION:
This experiment is about the hardware implementation and analysis of the operation of TTL and CMOS logic gates. The type of logic gate tested in this experiment is the inverter. The TTL inverter logic gate is the 74LS04 Hex Inverter; the CMOS inverter logic gate is the 74C04 Hex Inverter . In the analysis part, the TTL and CMOS logic gates are examined of the following properties: (1) transfer function, (2) effect of floating inputs, and (3) propagation delays. Additionally, for the TTL logic gate, the propagation delay hazards are examined.
The transfer function relates the input voltage to the output voltage and the loop current. In this experiment, the input voltage is varied from 0 to 5V and the corresponding output voltage and current are measured. By tabulation of the results and graphical output, the transfer function will define how the inverters would react to any particular voltage input.
Floating input is a condition wherein the inverter is powered up but the input port is disconnected or is not fed any voltage input. In this experiment, the inverters are tested of their response to floating inputs. This will determine what the default output voltage is for the inverters.
Propagation delay is the measure of how much time the input voltage needs to travel across the internal circuitry of the inverter until it is converted to output voltage on the output port. The propagation delays for the two types of inverters, TTL and CMOS, are compared. The propagation delays are measured by cascading 6 inverters and measuring the total and average delays between the inputs and the outputs. Moreover, the behavior of the TTL chip is observed regarding the effects of increasing propagation delay.
This experiment will provide a fundamental background about the operations of the TTL and CMOS inverters mentioned. The input/output relationships and the propagation delays are two essential properties of these devices that must be considered in the design and integration of these devices in practical applications. With the knowledge of the transfer function, the inverter circuits can be adjusted such that the inverter would output the appropriate voltage HIGH or LOW for particular values of the input. With the knowledge of the propagation delay, the limitations can be properly addressed in order to avoid undesirable output voltage behavior.
APPARATUS:
Electronic Laboratory Equipment.
PROCEDURE:
As per Laboratory Manual.
RESULTS:
PART A: INVERTER GATE TRANSFER FUNCTIONS
GRAPH 1: TTL TRANSFER FUNCTION
TABLE 2: CMOS TRANSFER FUNCTION
GRAPH 2: CMOS TRANSFER FUNCTION
PART B: EFFECT OF FLOATING INPUTS
TTL GATE
CMOS GATE
PART C: PROPAGATION DELAYS
PROPAGATION TRANSITION DSO WAVEFORM OF THE TTL GATE:
DELAY FOR SIX GATES: 36 ns
DELAY FOR SINGLE GATE: 6 ns
PROPAGATION TRANSITION DSO WAVEFORM OF THECMOS GATE
DELAY FOR SIX GATES: 44 ns
DELAY FOR SINGLE GATE: 7.3 ns
PART D: PROPAGATION DELAY HAZARDS
BOOLEAN EXPRESSION FOR CIRCUIT
PROPAGATION DELAY HAZARD DSO WAVEFORM
DISCUSSION:
The transfer functions went as expected. For low levels of voltage, the inverters detect logic LOW, thus the outputs are logic HIGH. When the input voltage reached a certain positive voltage, the inverter starts detecting logic HIGH, thus the outputs are logic LOW. The main difference between the two types is the level of the voltage HIGH; the TTL inverter detects logic HIGH at a very low 1.2 V, while the CMOS inverter detects logic HIGH at 2.8 V. In terms of current, the TTL transfer function has relatively constant current at any input voltage. The TTL transfer function has sudden increase in current in the input voltage range of 2.4V to 2.8V. Apparently, this is also the region wherein the inverter starts detecting logic HIGH.
For the TTL inverter floating input, the output is 0.02V, which is registered as logic LOW. Thus, the floating input is detected as logic HIGH. This is considered the default value of the inverter input: the input is normally HIGH. For the CMOS inverter floating input, the output is 2.7V, which is located in the transition region. Thus, the logic of the output is undefined: it cannot be determined whether it is HIGH or LOW. This becomes problematic when used in practical applications because it is more desirable that the inverter’s response is binary—either HIGH or LOW, no middle ground. Thus, the CMOS inverter should operate away from this region where it cannot automatically assign logic HIGH or LOW.
In terms of propagation delay, the TTL inverter has a lower propagation delay compared to the CMOS inverter. Effectively, the TTL inverter has a faster response compared to the CMOS inverter. If the application is designed to operate in the nanoseconds range, the propagation delay should be a consideration in choosing between these two types.
With the given logic gate circuit, the output signal shows a bizarre behavior. The expected output is logic LOW, but the output starts at logic HIGH, then transitions to logic LOW after a brief period of time (approximately 44 ns). This behavior is caused by the propagation delay across the gates. Initially, the AND gate detects two normally HIGH inputs, which results to a HIGH output. Then, when the input voltage has travelled through the 5 inverters, the AND gate suddenly detects a logic LOW on one of its inputs. Thus, the output transitions to logic LOW. The 44 ns is equivalent to the propagation delay for 6 gates (5 inverters, 1 AND gate), as shown in the PART C results.
CONCLUSION:
The transfer function and propagation delay of the TTL and CMOS logic gates were successfully measured and analyzed experimentally. It was observed that the TTL logic gate had a smoother transition in the transfer function, and also a faster response in terms of propagation delay.
REFERENCES:
Fairchild Semiconductor 2002, MM74C04 Datasheet, viewed 22 April 2016, <https://www.fairchildsemi.com/datasheets/MM/MM74C04.pdf>.
Texas Instruments 2004, SN74LS04 Datasheet, viewed 22 April 2016, <http://www.ti.com/lit/ds/symlink/sn74ls04.pdf>.
