Module 6
Design of Synchronous Sequential Counters
ELEC201
Digital Electronics
Partner Name:
Objectives
The objectives of the laboratory were as follows:
Introduction
Counters are categorized under Medium Scale Integrated sequential logic circuits. The counter circuits consist of several flip-flops that have been cascaded together and may also have an additional combinational circuit. They are mostly used in application that involve counting where they are applied in either the measurement of time that elapses between two instances that are not known, or the measurement of the frequency of a particular signal.
There are several types of counters such as those given below
- Asynchronous counters
- Synchronous counters
An asynchronous counter is also referred to as a ripple counter or a serial counter is one which consists of flip-flops that are arranged in a cascade manner where the output of a particular flip-flop is used as the clock of the next flip-flop in the cascade. The number of flip flops in the set up will determine the modulus of that particular counter. The modulus of a counter is the number of states that the counter must go through before the repetition of the sequence. The disadvantage with this arrangement is that, there is a large amount of propagation delay involved, which may not give good results. The more the number of flip-flops then the greater the delay.
A synchronous counter is also called a parallel counter whereby all the involved flip-flops change their state at the same instant in synchrony with the signal of input clock. One input clock is applied to all the flip-flop. The advantage of this kind of arrangement is that the propagation delay is reduced to only the propagation delay of the individual flip-flops.
The modulus of a counter (MOC) is the number of different logic states that a counter undergoes before going back to the initial state. A counter that is n-bit will have a 2n states.
In determining the number of flip-flops that are required to make a counter, obtain a number that is equal or greater or equal to the modulus required and is an integral power of two. This can be given by the formula
(2N-1+1≤modulus ≤2N
Where N is the minimum number of flip-flops that can be used.
Procedure
The state table
Up counter, X=1
Karnaugh Maps simplification
J0 K0
J0=K0=1
J1 K1J1=K1= Q0
J2 K2
J2=K2= Q0 Q1
J3 K3
J3=K3= Q0 Q1 Q2
Down Counter, X=0
Karnaugh Maps simplification
J0 K0
J0=K0=1
J1 K1
J1=K1=Q0
J2 K2
J2=K2=Q1Q0
J3 K3
J3=K2=Q2Q1Q0
After the simplification of the equations, it is found that the down counter is almost similar to the up counter only that the outputs of the flip flops are complemented.
Therefore, a circuit that has a control signal, X, can be used to implement the synchronous up/down counter. The configuration is in such a way that when X=1, it is an up counter and when X=0 it is a down counter.
The Excitation tables of a J-K flip flop
It is shown in the table shown
The circuit obtained will be as shown in the diagram below
Figure. The circuit of a synchronous up/down counter using J-K flip flops
MultiSim simulation results
When X=1, the result is as shown in the figure below
Discussion/ Conclusion
A control signal is provided for the selection of desired action that is up counting or down counting. A NOT gate is used to negate X control signal so that when the signal is 0, the one feeding the down counter operation is logic 1 while that of up counter operation is 0. When the X control signal is 1, the up counter operation is enabled while the down counter operation is disabled.
The simplified equations for the down counter are the complement of the equations of the up counter. This is obtained by using the negated output of the flip flops, Q. Both the outputs of the flip flops are made to be the inputs of two AND gates. These and gates are selected by the appropriate control signal.
The OR gate is provided in order to allow the selected operation to proceed to the next stage.
The up/down counter that is developed is simple and works as shown by the simulation diagrams.
Fig. Multisim simulation result when X=1
This is a timing diagram of an up counter when the control sign, X=0
When X=0 , the result is as shown in the figure
Fig. The Multisim simulation result when X=0
The timing diagram above shows that that a down counter is obtained from the circuit when the control signal, X=0
References:
Fuhrer, R. M., & Nowick, S. (2001). Sequential optimization of asynchronous and synchronous finite-state machines: Algorithms and tools. Boston: Kluwer Academic Publishers.
Nair, B. S. (2006). Digital electronics and logic design. New Delhi: Prentice-Hall of India.
