REPORT NUMBER 2
The report presented is the sole work of the author. None of this report is plagiarized (in whole or part) from a fellow student's work, or from any un-referenced outside source.
AIM:
The purpose of this experiment is to:
Investigate the voltage switch over the points required for logic high or low levels.
Prove experimentally different Boolean laws and logic theorems.
Use different logic laws and theorems, to simply a combinatorial logic circuit.
INTRODUCTION:
This level detector circuit is based upon a LM311 Digital Comparator. This digital comparator is a device that produces an output level, either high or low depending on the input comparator terminal (positive or negative) that has greater voltage level. Individual lvel outputs light for particular input voltage levels.
A Boolean function is that algebraic expression that is formed by the use of binary constants, binary variables as well as Boolean logic operation symbols. The basic Boolean logic operations include the AND function, that is, the logical multiplication, the OR function, that is, logic addition and the NOT function, that is logical complementation. The Boolean function is converted into a logic diagram that is composed of the AND, OR, and NOT gates.
APPARATUS:
Electronic Laboratory Equipment
PROCEDURE:
The below diagram was first drawn. With an input voltage of zero to 5 volts was set, the status of the output level1, level 2, and level 3 were determined from different input voltages. The exact voltages of the switch over the points were determined for each logic level output. The indications on the LEDs were recorded. The voltage ranges defining high, medium and low digital states were determined. The above circuit was verified if it was correctly indicating the input voltage. Afterwards, the procedure below proceeded.
Circuit F was connected and the truth table of F obtained. Also, circuit Z was connected and a truth table obtained. The truth tables of F and Z were compared if they were similar. Boolean operations were used to verify equation F if it can be obtained from equation Z. the advantages of NAND/NAND gate combination were described. The reason for using De-Morgan’s law was used to simplify the circuit.
In part C, NAND gate circuits (CIRCUIT 1 and CIRCUIT 2) were connected. The truth table for each was determined. The standard gates (AND, OR, NAND, NOR and EX-OR), were compared which gate matched the particular NAND gate circuits. The universal property of the NAND gate were explained.
In part D, the circuit was redrawn using common logic symbols. Boolean operations were used to derive the final logic function of Z. Boolean algebra was used to simplify the logic function of Z to its reduced/minimized form. A complete truth table of ZZ was drawn. The circuit was simplified using a karnaugh Map in order to obtain AND/OR and NAND equivalent minimized circuits. The Boolean algebra simplification and the K-map simplification produced were verified if they were producing the same results. The simplified NAND/NAND equivalent circuit was constructed and the simplified circuit verified if it produced the same truth table derived in the initial circuit.
RESULTS:
PART A: LOGIC LEVELS
CIRCUIT DIAGRAM
WIRING DIAGRAM
THRESHOLD LEVELS
PART B: DE-MORGANS LAW
CIRCUIT DIAGRAM OF CIRCUIT ‘F’
WIRING DIAGRAM OF CIRCUIT ‘F’
2. TRUTH TABLE
CIRCUIT DIAGRAM OF CIRCUIT ‘Z’
WIRING DIAGRAM OF CIRCUIT ‘Z’
4. BOOLEAN ALGEBRA CONVERSION OF CIRCUIT Z TO CIRCUIT F
PART C: UNIVERSAL PROPERTY OF THE NAND GATE
CIRCUIT DIAGRAM OF NAND CIRCUIT 1 (OUTPUT Z)
WIRING DIAGRAM OF NAND CIRCUIT 1 (OUTPUT Z)
TRUTH TABLEOF NAND CIRCUIT 1
NAND CIRCUIT 1 (OUTPUT Z) IS SIMILAR TO: Z COMPLEMENT
CIRCUIT DIAGRAM OF NAND CIRCUIT 2 (OUTPUT X)
90WIRING DIAGRAM OF NAND CIRCUIT 2 (OUTPUT X)
TRUTH TABLE OF NAND CIRCUIT 2
NAND CIRCUIT 2 (OUTPUT X) IS SIMILAR TO: X COMPLEMENT
PART D: COMBINATORIAL LOGIC
1. COMMON LOGIC CIRCUIT OF Z:
2. CIRCUIT Z BOOLEAN FUNCTIONS:
Z= ___ x'y'z' + x'y'z + x'yz' and F2(x,y,z) = x'yz' + x'yz + xyz' + xyz ____________________________________________________________________
3. BOOLEAN ALGEBRA SIMPLIFICATION OF CIRCUIT Z
4. TRUTH TABLE OF CIRCUIT Z
5. KARNAUGH MAP SIMPLIFICATION OF Z:
AND / OR CIRCUIT DIAGRAM OF SIMPLIFIED CIRCUIT Z:
NAND CIRCUIT DIAGRAM OF SIMPLIFIED CIRCUIT Z:
WIRING DIAGRAM OF SIMPLIFIED NAND CIRCUIT Z
TRUTH TABLE OF SIMPLIFIED CIRCUIT Z
DISCUSSION:
It is actual that the primary functions of AND, OR, NAND, NOR and NOT are not sufficient enough to perform complex digital functions. The gates are the basis of building more complex logic circuits constructed using different combinations of gates that are referred to as combinational logic. Complex functions normally start as a Boolean equation; the logic circuit is implemented directly from the equation. The logic designer implements a logic function using as few logic gates as necessary. The cost is reduced, and fewer parts become more reliable making it easier to build and repair.
Circuit minimization in Boolean algebra is the achievement of the smallest logic circuit, that is, the Boolean formula representing a given Boolean function or even a truth table. Minimization helps to reduce complicated circuit where elements take large physical space and become complex. Minimization intents to so solve this problem. Different logic gate circuit symbol standards are very important as they show the different components in a logic circuit with much ease.
In a logic circuit, both low and high states Rae specified with voltage ranges. For instance, a logic high ranges between 2 to 5 volts while the low range from 0 to 1 volt. Voltage outside this range are referred to as invalid; they occur during a fault in that case. In the experiment, the k-map of F was found to be the same as that of the Z.
A NAND gate is a special type of logic gate that is referred to as a universal gate; a NAND can create any logical Boolean expression once designed in the proper way.
CONCLUSION:
The exercise/experiment was a successful one. Our knowledge of logic levels, laws, and theorems was simplified and understood well. Different k-maps of logic gates were implemented and verified. The reason why some gates have particular characteristic was synthesized and the results outlined as shown above. Arguably, the whole exercise was a successful one.
REFERENCES:
Angell, R. B. (2002). A-logic. Lanham, Md, University Press of America.
Fox, H., & Bolton, W. (2002). Mathematics for engineers and technologists. Oxford, Butterworth-Heinemann. Web site last updated: 16/4/11, Viewed: 14 April 2016. <http://public.eblib.com/choice/publicfullrecord.aspx?p=314011>
