Introduction
Today, the number of hardware and software application is skyrocketing, thanks to Electronics. Since the discovery of Semi-conductors, and their applications, technology has seen an exponential growth. In particular, the invention of logic gates has played a major role in the development of high-end technology in today’s digital world. It all started with the advent of Integrated Circuits, which were modeled to perform specific logic. Gradually, basic logic turned into more complex ones, which resulted in programs, and branched into the popular field of Computer Science. And then, with the integration of hardware and software, it became possible to make programmable hardware components [1]. Starting from application specific modules, today we have generic modules, whose functions are designed by the customer. This design can be altered as and when required, i.e., the modules are re-programmable. One such technology is the FPGA (Field-Programmable Gate Array) that can be coded using hardware description languages like VHDL. This paper analyzes the network emulation in FPGA using VHDL, and also gives the background necessary to understand the same.
Background
Programmable Logic Devices (PLD)
Logic gates have fixed functions; therefore, a combination of logic gates also performs very specific operations. Though, these gates are useful; they are not versatile, which is an important requirement in any field. With this purpose, components capable of programmable logic, called PLDs, were designed. In other words, PLDs are configurable digital circuits. The following are the different modules that have evolved to the next levels:
- Programmable logic Array (PLA) – This consists of a programmable AND gate array, which in turn, is linked with a programmable OR gate array. These arrays may be conditionally programmed so as to get the desired output.
- Programmable Array logic (PAL) – These are transistor based arrays, which use a combination of programmable AND, and fixed OR logic, which yields the SOP (sum of products) type binary logic equations as outputs, based on feedback (can be synchronous or asynchronous).
- Generic Array Logic (GAL) – This is similar to PAL, with one additional feature – it is reprogrammable, i.e. the logic can be erased and redesigned.
- Complex Programmable Logic Device (CPLD) – The above PLDs are used for limited logic; they contain a maximum of a hundred gates. For more complicated logic, the number of components required increases. CPLDs have hundreds to even hundreds of thousands of components, linked together, to enable programming of complex logic.
- Field-programmable gate arrays (FPGA) – These devices work on a totally different principle – they use grids of logic gates. They also have more far reaching applications than CPLDs in that; they contain more components and can be used as basic modules in microprocessors. Their working and applications are dealt with in more detail in the subsequent sections [2].
ASICs and FPGAs
Applications-specific integrated circuits are again rigid, in the sense their logic is permanently fixed by the manufacturer. Initially, ASICs had around 5000 components (gates), capable of quite complex network topologies. As technology continued to improve, everything became possible using smaller sized devices. For example, the same ASICs can now accommodate over a 100 million gates and are used in various memory blocks including flash memory, EEPROM, ROM, etc., and in microprocessors. The design of an ASIC involves the use of an HDL (hardware description language). Examples of HDLs include VHDL and Verilog.
Both FPGA and ASIC are designed using HDLs, and are capable of more or less equal complexity in terms of functionality. However, the main difference between an FPGA and an ASIC is that the former is programmed by the customer rather than the manufacturer. Further, FPGAs make use of high speed I/O modules and bidirectional data buses. The biggest challenge then, is the verification of timing and validation data within the setup and hold times. This is achieved by careful internal allocation by the process of floor planning.
FPGAs can be understood as technology for hardware prototyping using standard parts. They also employ programmable logic blocks and links, making them versatile. Almost any application carried out by an ASIC can be achieved using an FPGA, and results in cost minimization in cases of low production volumes and/or smaller designs. This is mainly because the NRE (non-recurring engineering) costs associated with an ASIC can typically go up to millions of dollars. So, on the whole, customer specific programmability, provision for partial reconfiguration of parts of the design, and low NRE costs are the factors that differentiate an FPGA from an ASIC and hand the former a clear advantage over the latter [3, 4].
Network emulation means the process of assessing a network, by simulating the network design to which specific input conditions can be applied. The response of the network then aids in analyzing its performance and improve the design. Generally, this is an iterative process, where the design is continuously modified till consecutive cycles result in the same deign.
As mentioned above, the design of FPGAs (hardware network emulation) is carried out using HDLs. Once the function of the FPGA is defined using schematics, a technology-mapped net list is created using an EDA (Electronic Design Automation) tool. Place-and-route is a process (uses a software) which then allows the net list to be accommodated in the FPGA architecture. Timing analysis simulation allows the user to then validate the map, and place-and-route results. Once all the verification is done, the binary file generated by the software, enables the FPGA to be configured, which is done by transferring the file through a serial interface, to the FPGA.
In a typical FPGA configuration process, the user initially simulates multiple stages of the design one by one. RTL (Register Transfer Level) is a design algorithm that models synchronous digital circuits with respect to the flow of data (digital signals) between the hardware components (registers), and the logic performed on these signals. This RTL abstraction is an important process in HDLs. It generates top level representations of a circuit, which can be used to derive the lower-level representations and finally the actual wiring.
Once the RTL description is ready in VHDL, it is simulated by generating test benches that emulate the network and observe results. The the design is mapped to a net list by the synthesis engine; the net list is then coded as a gate level description. The simulation is the repeated at this level, to verify the synthesis process. When it cleared to be free of errors, the design is placed on the FPGA. At this juncture, propagation delays may be included, and the design tested again by simulation. During such a process, values are back-annotated (fed back) to the net list. The overall design flow is categorized into two: Altera and Xilinx. The flow charts for these are shown in Figure 1 and Figure 2 respectively [5, 6].
Figure 1: Altera design flow
Figure 2: Xilinx design flow
More about VHDL
The block diagram for the working of VHDL is shown in Figure 3, and its file structure is shown in Figure 4. VHDL is capable of handling the parallelism that is inherent in hardware layouts. When the VHDL translation of gates and wires is mapped onto PLDs such as a CPLD or an FPGA, the actual hardware gets configured; it is not the VHDL code that is executed like in the case of a processor chip [7].
Figure 3: VHDL block diagram
Figure 4: VHDL file structure
Conclusion
VHDL is a popular hardware description language for EDA, and is used to describe the functionality of digital/mixed signal systems such as FPGAs. VHDL IDE can be used to design network topologies for hardware implementation (for example, on an FPGA), by generating the required RTL schematic of the circuit, which is then verified by simulating the design by means of test benches. In order to get correct test benches, it is important to define the inputs accurately. For example, in the case of a clock input, an iterative statement or a looping is necessary.
VHDL, like other languages, is as complex as assembly languages. In order to reduce the complexity in using HDLs, companies are now looking to introduce alternative languages that can raise the abstraction level of the existing language. For example, National Instruments (NI) has provided an FPGA add-in module option in its famous graphical programming language, LabVIEW. This module can target and code FPGA hardware.
References
- Rabaey, Jan M., Anantha P. Chandrakasan, and Borivoje Nikolic. (2002). Digital integrated circuits. Vol. 2. Englewood Cliffs: Prentice hall.
- Pellerin, David; Michael Holley (1991). Practical Design Using Programmable Logic. Prentice-Hall. p. 15. ISBN 0-13-723834-7.
- Kevin Morris (23 November 2003). "Cost-Reduction Quagmire: Structured ASIC and Other Options". FPGA and Programmable Logic Journal.
- Golshan, K. (2007). Physical design essentials: an ASIC design implementation perspective. New York: Springer. ISBN 0-387-36642-3.
- Frank Vahid (2010). Digital Design with RTL Design, Verilog and VHDL (2nd ed.). John Wiley and Sons. p. 247. ISBN 978-0-470-53108-2.
- Chu, Pong P. (2008). FPGA prototyping by VHDL examples: Xilinx Spartan-3 version. John Wiley & Sons.
- Navabi, Zainalabedin. (1997). VHDL: Analysis and modeling of digital systems. McGraw-Hill, Inc.
