555timer
Introduction
The 555 integrated circuit (chip) is used in a variety of timer and oscillator applications. A 555 timer is used to provide time delays and oscillations and as a flip-flop element. The device has additional terminals provided to trigger or resetting purpose (Nair, 2006). During the time delay operation mode, time is precisely controlled by an external resistor and capacitor. While working as an oscillator, the duty cycle and the frequency are accurately regulated by two external resistors and a capacitor (Brumbach, & Clade, 2003). 555 is triggered and reset on falling waveforms. A typical 555 timer IC is shown in figure 1 below.
Figure 1. Pin out a diagram of a 555 timer.
2. Design
2.1 Connection of terminals (pins)
The 555 timer is extremely versatile. It's used to construct a variety of circuits. It is as well simple to assemble in a breadboard. Mostly, the timer is used in a stable mode to yield a continuous series of pulses. The timer is used to make one-shot (monostable circuit). It sources or sinks 200 mA output current. The timer can drive a variety of output devices as well.
2.2 Astable circuits
When a 555 timer oscillator of specific and mark to space ratio is desired, the method involves calculation of the needed frequency and time of discharge as well as charge time. The design specified the maximum resistance to being used with the variant of 555 timers usually 10 to 20 megaohms. To avoid errors between the actual and the calculated frequency, a one megaohm resistance is used rather. In this design, R1 determines the minimal total resistance value in the combination of R1 and R2. The R1/R2 junction is connected to pin six while trigger input to pin R1.
In the simulation, pressing the Y-button opens the simulation program on a PC. In a 555 timer, resistor R1 and R2 determine the frequency and the repetition rate. The design frequency is:
.1
The period, t. of the produced pulses is given by,
HIGH and LOW times of the pulses are given as and respectively. The duty cycle is expressed as a percentage while the mark space ratio is expressed as.
If the desired duty cycle is less than half, that is less than 50% the value of R2 must be greater than the value of R1. Before calculating the frequency of the timer, R1 –s normally set at 1kiloohm. This helps to provide the output pulses a duty cycle of about 50%. On the other hand, if R1 is greater than R2, therefore the duty cycle is greater than 50 percent. In the design, it is appropriate to work with fundamental units as shown in Table 1 below.
In the selection of A stable component, it is easy to select the right values for the 555 timers. In an extended duty cycle astable, a standard astable circuit involves an addition of diode parallel with R2 adding a dramatic effect to the circuit’s behavior. Timing capacitor is filled through R1 and at the same time emptied through R2. The components (resistors and capacitor) used in the circuit, R1=1k, R2= 3k, and a timing capacitor of are C1 = 8.8nF. When the diode is set, and the LED is ON, the HIGH time is 0.69(0.001x0.0088) = 6.072microseconds. In this case, the LOW time is expected to be longer; 0.69(0.003x88)= 0.01822 milliseconds.
2.3 Minimum component astable
.3
The duty cycle of the circuit is fixed at 50 percent with both the HIGH nad LOW times supposed to be equal. Practically, HIGH time is longer than the LOW time. This is because the maximum voltage attained by the output pulses is lower than the power supplied to the circuit.
2.4 RESET circuit
If pin 4 (the RESET input) is HIGH, the 55 circuit normally works, if it’s LOW, the output pulses stop. This configuration can be investigated by connecting a switch/pull down resistor voltage divider across pin 4.
2.5 CONTROL VOLTAGE input
When a control voltage is applied to pin 5, the timing characteristics of the device is altered. In an astable mode of operation, the control voltage is varied from 1.7 volts to that of the power supply voltage. At this time, an output frequency larger or lower than the frequency configured by R1, R2, and C timing network is produced. The CTRL VOLTAGE input is used to build an astable of frequency modulated output.
2.6 Monostable circuits
In a monostable (one-shot) design, 555 produces one pulse when triggered. The circuit is triggered by falling edge mechanism – sudden transition from HIGH to LOW. A trigger pulse is generated by pressing a button, a shorter duration/pulse than the expected output pulse given as;
.4
3. Calculations
Frequency = 41 kHz.
Duty cycle = T = Ton + Toff
T =
D = 0.245
Resistors =
Since R1 = 1 kiloohms
Then R2 is equal to:
Capacitors =
C = 8.6 nF
The filter components of C3 and C4.
The overall circuit diagram of the timer is was as shown in figure 2 below.
Figure 2. Overall circuit diagram of the 555 Timer
4. Simulation
When the circuit is allowed to run on the PC, the ultimate wave on the window is a square wave. The timing interval begins when the trigger input, (TRIG) goes lower than a third the input voltage. When this happens, the 555 timer output goes HIGH. It then waits for the threshold (THRD0 to attain two-thirds of the input voltage. When the capacitor is charged, the threshold input arises slowly until it attains the needed level. At this point, the timing interval ends, and the output goes low. The capacitor is discharged through the pin “DIS”. After the capacitor is discharged fully so that the timer reaches 3.33V, a new timing interval starts. A square wave is seen to be the result. Figure 4 below shows results of the simulated 555 timer circuit.
Figure 4. A simulated 555 timer using the MultiSim software
In the above simulation, the values are the same. This is because the MultiSim enables the user to build their circuit with any values of their choice.
5. Breadboarding of the 555 Timer
Here, the required parts (components) were: Breadboard, 12v Battery (Vcc), Battery clip, Jump Wires, 555 Timer, a Capacitor 1μF, two resistors (1k Ohm, brown, black, red and 3k Ohm yellow, purple, yellow), 741 FILTER, and an L.E.D. the above components are shown in figure 5 below.
Figure 5. a) Breadboard, b) 12v Battery, c) Battery clip, d) Jump Wires, e) 555 Timer, f) Capacitor 1μF, g) resistors h) L.E.D
The above components were assembled to form the below assembly.
Figure 6. 555 Timer assembly
In the breadboarding exercise, the left and right sides of the breadboard were electrically connected with the 12 volts battery, the Vcc pin of the 555 timer was set at the top were a positive terminal of the battery was connected and the ground connected to the negative terminal of the battery. The center of the breadboard was considered as the main component of the assembly were the resistors, capacitors, and the LED were connected. After examining the schematic diagram of the circuit, the physical simulation of the Timer was compared with the simulation conducted on a multisim software. There was the difference in the frequency of both cases. The table below illustrates the comparison
The output of the circuit was viewed in the oscilloscope as shown in figure 7 below.
Figure 7. The output of the 555 Timer on an oscilloscope.
As it can be seen on the right side of the oscilloscope screen, the duty cycle of the circuit was found to be 26.5 while the frequency of pulses was 32.03 kHz. Compared to the simulated circuit on the Mulitism, this circuit could have suffered imperfections regarding cabling, heating of cables compared to the perfect connections in the multisim. The graphs were also different; sharp square waves were observed from the multisim circuit. On the other simulation, the square waves were seen to ripple at the top.
5. Summary
The 555 timer IC has got three resistors. If the resistors are equal, they form a voltage divider that provides voltage references at one-third and two-thirds of Vcc. When the power supply is connected to the astable circuit, the timing capacitor is discharged, at pin 2, the voltage is zero while the output of the timer is HIGH (Bali, 2008). The capacitor starts to charge through the resistors R1 and R2.when the voltage of the capacitor exceeds one-third of the Vcc; the comparator output snaps a new level. When the voltage exceeds two-thirds of Vcc, the second comparator output locks a new level. Here, the flip-flop changes the state, and its output becomes HOGH, the output of 55 goes from HIGH to LOW.
References
Bali, S. P. (2008). Linear integrated circuits. New Delhi, Tata McGraw-Hill.
Brumbach, M. E., & Clade, J. A. (2003). Industrial maintenance. Clifton Park, NY, Thomson/Delmar Learning.
Carr, J. J. (1996). Linear IC Applications: a designer's handbook. Boston, Mass, Butterworth-Heinemann.
Nair, B. S. (2006). Digital electronics and logic design. New Delhi, Prentice-Hall of India.
